Job Information
Intel 3D-IC STCO Silicon Architect in Helena, Montana
Job Description
The Role:
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System.
Responsibilities include, but are not limited to the following:
Design definition to establish STCO (System Technology Co-Optimization)
3DIC prototypes across market segments.
Identify 3D architecture configurations and die partition for best System Co-optimization PPAC.
IP configuration, RTL coding, Verilog system simulation, pre and post silicon validation and system simulation
Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.
Understands all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Design optimization of 3D advanced silicon and package technology features to enable strong product differentiation.
Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.
The candidate should also exhibit the following behavioral traits and/or skills:
Excellent analytical and problem-solving skills.
Strong verbal/written communication skills.
The future of Moore's Law: 3D-IC
https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html
https://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/
https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum:
Master's degree in Electrical or Computer Engineering with 6+ years of experience in the following areas:
Experience in SI power-on, performance and/or yield analysis
Pre-silicon and post-silicon validation. Knowledge and expertise in SORT test program development and/or execution
Design for Test (DFT) and Design for Debug (DFD), ATPG, MBIST, etc.
Micro-architecture trade-offs and Logic design
Data analytics skills in on or more of: JMP, Python, R or similar tools.
Preferred:
Experience with ARM-based Systems.
3D Silicon and 3D packaging technologies. Knowledge of semiconductor process flow
Design Methodologies for optimal Performance Power Area Cost (PPAC) in advanced technologies.
Physical Design EDA tools, design reference/sign-off flows and EDA vendor engagement.
Circuit design and silicon technology.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations
US,Santa Clara
Covid Statement
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, California: $156,410.00-$250,410.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.