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Intel IP Logic Design Engineer - Graduate Intern in Helena, Montana

Job Description

The Foundational Security Hardware team is looking for future technical leaders and experts. Position requires knowledge in digital logic design, computer architecture, and/or exposure to pre/post-silicon validation. Candidate will be responsible for logic design of different blocks in the Security IP team.

In this role responsibilities include, although not limited to:

  • Defining and implementing the design in System Verilog.

  • Applying various strategies/tools/methods.

  • Checking the design for synthesizability, DFX, clock crossing, power, performance implications.

  • The candidate must work closely with Architects, Micro-architects and Validation teams in determining the proper implementation strategy for new design, defining and feedback on specifications, develop Open Box Coverage plans, review design collateral for efficiency/coverage.

In addition to the qualifications listed below, the ideal candidate will demonstrate the following traits:

  • Excellent communication and organization skills are critical.

  • Teamwork.

  • Technical leadership skills.

  • Passion for design tools and methodologies.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Requirements:

The candidate must be pursuing a Master's or Ph.D. in Electrical Engineering or Computer Engineering.

6+ months of experience in:

  • Digital logic design tools and methodologies including: System Verilog, Perl, VCS/Synopsys simulators, Lint, Synthesis, Clock Domain Crossing tools, DFX Scan and Power.

Preferred Requirements:

  • Knowledge of critical PC IO subsystems (e.g. PCIe, USB, SATA, UART, SPI ...).

  • Knowledge of HW/SW Security mechanisms and cryptography.

  • Knowledge of IO Controllers and Design and worked with standard buses / bridges such as AHB / OCP / AXI.

  • Knowledge of Low power / High Performance Designs and Practices.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US,Santa Clara

Covid Statement

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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